As is well known, reading the contents of cells in a semiconductor integrated electronic memory device is possible by means of a predetermined sequence of operations referred to in the art as the reading cycle.
A reading cycle begins with the memory address of data to be read being presented to the input terminals of the memory circuit. An input stage detects a change in the status of the addresses present on such terminals to thereby initiate a reading operation.
Row and column decoder circuits select the memory word that has been addressed.
The states of the cells contained in this memory word are sensed by a read amplifier, commonly referred to as the sense amplifier. The data sensed by the sense amplifier is then output through an output buffer stage.
Each of the above reading cycle phases must have a predetermined duration and be compatible with the memory access times set up by the memory circuit specifications.
All of the various phases of a reading cycle are clocked by synchronization pulses derived from a single main pulse referred to as the ATD (Address Transition Detection) pulse. The ATD pulse is generated within the memory circuit each time that a switching of address is sensed on the input terminals.
In general, the generation of the ATD pulse is entrusted to a NOR structure whose output is normally at a high logic level.
On the occurrence of a change in logic level, even at just one of the input terminals, the NOR structure will switch its output to allow a terminal, from which the ATD pulse is delivered, to be discharged to ground.
The accompanying FIG. 1 depicts schematically circuitry for generating the ATD signal, in accordance with a first prior art structure.
FIG. 1 shows circuitry 1 which comprises a plurality of input buffer stages 2 each associated with a respective one of a plurality of address input terminals. The input terminals are designated PAD&lt;0&gt;, . . . , PAD&lt;9&gt;.
Each of the input buffer stages 2 has at least one buffered output 3, that is, an output delivering a signal buff-inp which is essentially a delayed replica of the signal present on the corresponding PAD. The structure shown in FIG. 1 is referred to as a concentrated NOR because all the outputs 3 of the stages 2 are connected to a single ATD pulse generating circuit 4 which implements a logical NOR function. The NOR circuitry 1 has an output 5 that delivers the ATD pulse as discussed below.
The ATD pulse generating circuit 4 has an output node 8 that presents an ATD signal and is coupled to an inverter 9 which outputs the ATD pulse at the output 10 of the NOR circuitry 1. The output node 8 is connected by a resistor R to a power supply Vcc and by a capacitor C to ground.
This NOR circuitry I always has at least one of its input terminals at a high logic level, such that its output 10 can be low whenever in a static condition. Therefore, the ATD signal (ATD .sub.-- Line) will be normally high and an upward ATD pulse will originate from a downward transition of the ATD signal due to the inverter 9.
As previously mentioned, the ATD pulse would only be generated on the occurrence of a transition in the logic state of one of the input terminals PAD&lt;0&gt;, . . . , PAD&lt;9&gt;. The accompanying FIG. 2 depicts schematically the structure of the ATD pulse generating circuit 4 for generating the ATD signal.
The ATD pulse generating circuit 4 comprises P-channel MOS transistors, designated M2, M4 and M7, which are highly resistive and, therefore. hardly conductive. The transistor M7 has its gate connected to ground, and thus, is always ON and holds the output node 8 of the circuit 4 at a high logic level, in cooperation with a stabilizing capacitor C1.
The transistors M2 and M4 are pull-up elements for respective CMOS inverters formed with corresponding pull-down NMOS transistors M3 and M5. The structure which results from the coupling of the inverters M2, M3 and M4, M5 is that of a latching register 11 which has outputs, Q and Q, the Q output being normally at a high logic level and the Q output being at a low logic level.
The ATD pulse generating circuit 4 also includes two highly conductive NMOS transistors M1, M6 coupled to one of the buff-inp signals output from one of the input buffer stages 2. A control gate of the transistor M1 receives the buff-inp signal directly while a control gate of the transistor M6 receives an inverted buff-inp signal from an inverter I, the ATD pulse generating circuit 4 also includes capacitors C2 and C3, which stabilizes the output signals Q, Q.
In addition, the ATD pulse generating circuit 4 includes a logical NOR gate 13 that receives as inputs the output signals Q, Q from the latch 11. During steady state, one of the output signals Q, Q will be that a high logic level, which causes the output of the NOR gate 13 to be at a low logic level. The low logic output of the NOR gate 13 to be at a low logic level. The low logic level fails to turn on an NMOS transistor M8 coupled between the output node 8 and ground. As a result, the ATD signal at the output node 8 remains at a high logic level.
On the occurrence of a transition of the input signal buff-inp from a high logic level to a low one, the first output, Q, of the latching inverter 11 is brought to a low logic level very quickly because MOS transistor M6 is highly conductive. The other output, Q, will take a little more time to change its state because the pull-up transistors M2 and M4 are highly resistive. Thus there will be a time when both these outputs are Q, Q at a low logic level.
With the Q and Q outputs connected directly to respective inputs of the NOR gate 13, the output of the NOR gate 13 will be driven to a high logic value, thereby turning ON the NMOS transistor M8.
Turning ON the transistor M8 enables discharging of the current through the transistor M7 to ground, consequently changing the ATD signal at the output node 8 to a low logic value effective to produce the ATD pulse.
The structure just described is duplicated in the ATD pulse generated circuit 4 at each of the input terminals; only the transistor M7 of the output node 8 and its capacitor C1 are shared by the entire circuit 4, and correspond respectively to the resistor R and the capacitor C shown in FIG. 1. Accordingly, whenever any of the input signal buff-inp changes state, the current through the transited M7 as grounded, which produces an ATD pulse.
While being in many ways advantageous and substantially achieving its objective, the generator circuit previously described has certain drawbacks, as specified herein below.
A stable duration for the ATD pulse cannot always be ensured on the occurrence of spurious switching pulses (noise) at the address input terminals.
This has an adverse effect on the memory access times because the circuit will also generate an ATD pulse in the presence of noise, but this short-duration pulse does not allow a correct reading of data from the memory.
A second known solution, depicted schematically in FIG. 3, provides for the association, with each input terminal PAD, of an input buffer stage 5 which also incorporates a portion of the foregoing ATD pulse generating circuit.
According to this prior solution, referred to in the art as the distributed NOR, each input buffer stage 5 is provided with a control output 6 whereat an ATD signal is developed. All the outputs 6 of the buffer stages 5 are connected to a single line 7, ATD-LINE, which is normally implemented as a metallization line running up to the output node 8. The output node 8 is also connected to the power supply Vcc through the resistor R and to the ground GND through the capacitor C.
A pulse ATD-PULSE is obtained from the output node 8 by the inverter 9, as in the example of FIG. 1.
When a logic level transition occurs on one of the input terminals PAD, the corresponding control output 6 is able to bias the line ATD-LINE 7 to ground. Being comparatively long, the line 7 has a resistance and intrinsic capacitance of relatively high value. Accordingly, if the switching affects all of the addresses in parallel, the line 7 will be discharged quite rapidly. Otherwise, if the switching only affects the farthest PAD from the output node 8, the line 7 will be discharged at a slower rate.
This prior structure shows, therefore, to be dependent on the number of the switched addresses. In fact, where the switching involves those address terminals which are physically the farthest, the circuit undergoes a delay due to the length of the metallization paths. This reflects on the stability of the ATD pulse duration in an adverse manner.
In practice, a different duration is obtained for the equalization period according to which terminal is being switched, and this worsen the memory access time during the reading phase.
An underlying technical problem of the instant invention is to provide a method and a circuit for generating an ATD signal, which have such respective functional and structural features as to obviate the drawbacks that are besetting the solutions offered by the prior art.